Wednesday, 10 July 2013

Openings for SMTS II – Logic Verification Engineering. Exp: 8-10 years. Apply @

·         Bachelor's/Master's degree in Electronics/Electrical Engineering
·         7+ years of verification experience
·         Significant experience in HVL based verification with 3+ years expertise in SV & OVM
·         Experience in assertion based verification and formal verification
·         Good understanding of memory technology and memory sub-system
·         Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex IP / SOC designs
·         Should have knowledge on all aspects of verification components &verification closure
·         Should have flair for documentation, defining/improving methodology and achieving productivity improvement
·         Ability to provide technical guidance & resolving technical conflictsdesired
·         Ability to communicate technical and project issues to business and technical senior management
·         Ability to lead, guide, mentor 1-2 member team

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