· Strong technical breadth in technologies such as DDR1/DDR2/DDR3, SERDES, processors, memory, wireless, low power design.
· Strong circuit design skills with exposure on IOs, Transceivers, Clocking, voltage regulators, PLL, DLL, CDR
· The candidate should have prior system level experience and understanding of signal integrity, noise, circuits and packaging challenges in DDR/Memory interfaces/Physical layers.
· Track record of design and mass-production of DDR/SERDES PHYs is a highly desirable.
· Track record of driving technical solutions across organizational boundaries and multiple technical disciplines is preferred.
· Experience working in and leading R&D and future technology development projects is also desired.
Strong communication skills (written, verbal and presentation) desired.