Microsoft Hiring Freshers/Exp in Hyderabad for Technical Service and IT – Apply Now FOr Details :http://jobs.careersadda.com/today-top-walkinsjobs/ For Govt Jobs :http://jobs.careersadda.com/all-govt-jobs-and-bank-jobs/

Microsoft Hiring Freshers/Exp in Hyderabad for Technical Service and IT – Apply Now

FOr Details :http://jobs.careersadda.com/today-top-walkinsjobs/

For Govt Jobs :http://jobs.careersadda.com/all-govt-jobs-and-bank-jobs/

System Verilog with OVM Expert @ Chennai with a Product Based MNC

Job Synopsis
	System Verilog with OVM Expert @ Chennai with a Product Based MNC Company:   Roland and Associates Experience:   5 to 10 yrs Location:   Chennai
	Job Description
	Job Description:- Role : ASIC Verification Engineer Experience :  4 to 10 Years Work Location : Chennai  Qualification : BE / BTech / BS / Mtech / ME / MS / MSC Language     : System Verilog Methodology : OVM is Must Strong domain knowledge on  Ethernet    EMail your resume to saku@roljobs.com  Role:   Testing Engineer Role Category:   Programming & Design Industry Type:   Semiconductors / Electronics Functional Area:   IT Software - Embedded, EDA, VLSI, ASIC, Chip Design Keywords:   ASIC verification, System Verilog, OVM
	Desired Candidate Profile
	Education:   (UG - B.Tech/B.E. - Any Specialization, Electrical, Electronics/Telecomunication) OR (PG - M.Tech - Any Specialization, Electrical, Electronics/Telecomunication, M.Sc - Any Specialization) AND (Doctorate - Any Doctorate - Any Specialization, Doctorate Not Required)
	Company Profile
	Roland and Associates
	US based product development Company.

Life changing opportunity for Design Engineers with once of the leading Product companies in Semiconductor domain

JD for the same:

1. Participate in a global team setting on the development of advanced microcontroller products.
2. Design/modify new or existing modules in RTL to incorporate new/additional functionality based on architectural description.

3. Perform functional & timing verification at RTL & Gate Level for complex modules working from an architectural description.
4. Perform Synthesis and timing analysis. Closely work with place and route engineer on timing closure.

3. 5. Run formal verification tools to verify the construction of gate level netlist.
6. Help APR engineer to create timing ECOs.
7. Generate & debug test vectors for silicon validation.

8. Debug of complex silicon issues.

9. Technical mentoring & supervision of junior persons.


Job Requirements:

The candidate must have B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred. 

Candidate must have 6 to 15 years of experience working in CMOS VLSI development capacity, preferably on products that incorporate microcontrollers for embedded control applications. Strong digital design skills and experience in verilog behavioral modeling is essential. Experience with Simulation tools (Modelsim, NC-Verilog, VCS), Synopsys tools such as Design Compiler, Prime Time, DFT compiler and Formality. Good understanding of Place and Route tools such as IC Compiler. Knowledge or experience of System Verilog, Perl and TCL is an added advantage.

The candidate will be working as a part of global VLSI design team. Strong communication skill & the ability to interface effectively with US team members is essential.

NOTE: 

1. Must have decent experience in Micro Architecture 
2. Only ASIC professionals and NO FPGA

If interested, please reply to this mail with your updated profile ONLY IF YOU MATCH THE REQUIREMENT.

You may reach me at nagm@volksconsulting.com or call at 9900548673

Senior Engineer / Engineer - Functional Verification ( Digital ) - IT

We have an urgent opening with one of our prestigious clients. Please find the details below:


Job Location : Ahmedabad
Designation: Sr Engg/ Engg Functional Verification Digital
Exp: 4-15 years

Job Description

Min 1 year exp in SV UVM is must
At least 1-4 projects done under his belt
Person shoul have expertise in functional coverage code coverage testplan development testcase writing and debugging

Other Skill Required:
Design Language: System Verilog, Verilog
Scripting: Shell, perl
General Purpose Language: C C++
Standardized Interfaces PCI-express

If you are interested for the same please send your resume asap.

Ph : +918826982266
manish@jenters.com
http://www.jenters.com

Huge Openings for Physical Design Professionals

Huge Openings for Physical Design Professionals !!!

About Our Client : 
Our client founded in the year 1994.
Our client is a product engineering & semiconductor services leader that fulfils Product Design & Development, Quality Assurance & Testing & Product Sustenance & Maintenance. 
Since 1994, Our client serves Telecommunications & Networking, Aerospace & Defense, Machine Vision & Imaging, Consumer Electronics, Security & Surveillance and more.
Our client ensures best-in-class product engineering & cutting-edge "concept to finish" innovation for its customers, affordably, reliably and on time.
Our client has executed more than 400 projects for 90+ clients globally, 15 of which are multi-billion dollar market leaders.
Our client has long standing partnerships with the world"s top 6 semiconductor companies and is a Platinum Design House Partner for Texas Instruments (TI).
Our client assumes full ownership of the Product Development Life Cycle, allowing it to infuse innovation at each stage of the PDLC, & enabling its clients to surpass competitors through shorter time to market & lower costs of ownership.
Job Description:

Mandatory Skills : Physical Design
Interview Mode: ( Technical )Telephonic & (HR) Video Conference

Job Location: Ahmedabad/Noida

If you are interested please send your updated profile to naveen@arsenteam.com. Please refer any of your friends with this same profile.