Saturday, 13 July 2013

openings for asic verification and design engineers.

Broadcom, Bangalore is Hiring!!
Broadcom is a company created by engineers with a vision. Everyone and Everything will be connected, at home, at work, and on the go. Broadcom will enable all of these connections and enhance the experience.
If you are interested to explore career opportunities with us share your resume with
Verification Engineers: 3-10 years (Staff I and above) [3 Different Positions ]
1.       ME plus 3 years, or BE plus 5 years, equivalent experience in ASIC design and verification.
•Experience in verifying designs at system level and block level.
•Experience using System Verilog, VMM or UVM.
•Familiar with System Verilog Assertions.
•Strong experience in ASIC design verification flows and DV methodologies.
•Networking domain knowledge (e.g. Ethernet, GFP, and OTN).

2.         BSEE/MSEE degree with 3+ years of working experience in Verification.
- Must have excellent knowledge and experience of ASIC design verification flows and methodologies.
- Good Knowledge in languages relevant to the ASIC verification process including Verilog, SystemVerilog, VERA, Unix Scripting, and C.
- Experience of SoC/Arm CPU sub-system verification, performance
- Good knowledge Arm architecture and debug interfaces like ETM, ETB, JTAG etc
- Good knowledge of ARM ISA, AHB, AXI, APB protocols
- Good knowledge of USB/HSIC, SDIO, NAND and DDR controller interfaces
3.       Ideal candidate will have a minimum of 6+ years of verification experience, coupled with strong understanding of logic design, design cycle, tools and methodologies as well as strong design debug skills. Other characteristics include: 
• Familiarity with verification tools and methodologies like UVM
• Verification experiences in high-speed serial interconnect protocols like Interlaken, XAUI, PCIe
• Proficient in Verilog and System Verilog concepts
• Knowledge in Networking system concepts
• Experience or familiarity in one or more of the following areas: 
o Hardware/Software co-simulation using C-models and Verilog
o Gate simulations and Formal verification 
o Functional coverage and code-coverage techniques and analysis
o Regression setup scripts (in shell, Tcl/Tk, Perl, etc.) 
• Familiarity with simulators like VCS, Questa, IUC and debug tools like Debussy is must
• Must be highly motivated and skillful at solving difficult technical problems
Please contact me at for more details!

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