Saturday, 3 August 2013

Senior Engineer / Engineer - Functional Verification ( Digital ) - IT

We have an urgent opening with one of our prestigious clients. Please find the details below:

Job Location : Ahmedabad
Designation: Sr Engg/ Engg Functional Verification Digital
Exp: 4-15 years

Job Description

Min 1 year exp in SV UVM is must
At least 1-4 projects done under his belt
Person shoul have expertise in functional coverage code coverage testplan development testcase writing and debugging

Other Skill Required:
Design Language: System Verilog, Verilog
Scripting: Shell, perl
General Purpose Language: C C++
Standardized Interfaces PCI-express

If you are interested for the same please send your resume asap.

Ph : +918826982266

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