JD for the same:
1. Participate in a global team setting on the development of advanced microcontroller products.
2. Design/modify new or existing modules in RTL to incorporate new/additional functionality based on architectural description.
3. Perform functional & timing verification at RTL & Gate Level for complex modules working from an architectural description.
4. Perform Synthesis and timing analysis. Closely work with place and route engineer on timing closure.
3. 5. Run formal verification tools to verify the construction of gate level netlist.
6. Help APR engineer to create timing ECOs.
7. Generate & debug test vectors for silicon validation.
8. Debug of complex silicon issues.
9. Technical mentoring & supervision of junior persons.
Job Requirements:
The candidate must have B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred.
Candidate must have 6 to 15 years of experience working in CMOS VLSI development capacity, preferably on products that incorporate microcontrollers for embedded control applications. Strong digital design skills and experience in verilog behavioral modeling is essential. Experience with Simulation tools (Modelsim, NC-Verilog, VCS), Synopsys tools such as Design Compiler, Prime Time, DFT compiler and Formality. Good understanding of Place and Route tools such as IC Compiler. Knowledge or experience of System Verilog, Perl and TCL is an added advantage.
The candidate will be working as a part of global VLSI design team. Strong communication skill & the ability to interface effectively with US team members is essential.
NOTE:
1. Must have decent experience in Micro Architecture
2. Only ASIC professionals and NO FPGA
If interested, please reply to this mail with your updated profile ONLY IF YOU MATCH THE REQUIREMENT.
You may reach me at nagm@volksconsulting.com or call at 9900548673
1. Participate in a global team setting on the development of advanced microcontroller products.
2. Design/modify new or existing modules in RTL to incorporate new/additional functionality based on architectural description.
3. Perform functional & timing verification at RTL & Gate Level for complex modules working from an architectural description.
4. Perform Synthesis and timing analysis. Closely work with place and route engineer on timing closure.
3. 5. Run formal verification tools to verify the construction of gate level netlist.
6. Help APR engineer to create timing ECOs.
7. Generate & debug test vectors for silicon validation.
8. Debug of complex silicon issues.
9. Technical mentoring & supervision of junior persons.
Job Requirements:
The candidate must have B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred.
Candidate must have 6 to 15 years of experience working in CMOS VLSI development capacity, preferably on products that incorporate microcontrollers for embedded control applications. Strong digital design skills and experience in verilog behavioral modeling is essential. Experience with Simulation tools (Modelsim, NC-Verilog, VCS), Synopsys tools such as Design Compiler, Prime Time, DFT compiler and Formality. Good understanding of Place and Route tools such as IC Compiler. Knowledge or experience of System Verilog, Perl and TCL is an added advantage.
The candidate will be working as a part of global VLSI design team. Strong communication skill & the ability to interface effectively with US team members is essential.
NOTE:
1. Must have decent experience in Micro Architecture
2. Only ASIC professionals and NO FPGA
If interested, please reply to this mail with your updated profile ONLY IF YOU MATCH THE REQUIREMENT.
You may reach me at nagm@volksconsulting.com or call at 9900548673
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